Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are typically constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductive, semiconductive, and insulative regions formed on the semiconductor substrate.
FLASH memory, also known as FLASH EPROM or FLASH EEPROM, is a semiconductor component that is formed from an array of memory cells. Data can be written to each cell is within the array, but the data is erased in blocks of cells. Each cell includes a floating gate transistor having a source, drain, floating gate, and a control gate. The floating gate transistor uses channel hot electrons for writing from the drain and uses Fowler-Nordheim tunneling for erasure from the source. The source of each floating gate transistor in the cells of a row in the array are connected to form a source line.
The cells are electrically isolated from one another by an isolation structure. One type of isolation structure used is a LOCal Oxidation of Silicon (LOCOS) structure. LOCOS structures are generally formed by thermally growing a localized oxidation layer between the cells to electrically isolate the cells. Another type of isolation structure used is a Shallow Trench Isolation (STI). STI structures are generally formed by etching a trench between the cells and filling the trench with a suitable dielectric material.
Some source line fabrication process utilize a patterned photomask that exposes a source region of the semiconductor substrate as well as a portion of the floating gate transistors in the array. The exposed areas are subsequently anisotropically etched and then subjected to an ion implantation process that forms the source line and the self-aligned source for each floating gate transistor. Although the etching process is non-selective to the materials comprising the semiconductor substrate and the floating gate transistor, the etching process removes a portion of the exposed semiconductor substrate and the floating gate transistor.
The removed portion of the semiconductor substrate forms a notch immediately adjacent the floating gate transistor. The notch adversely affects the floating gate transistor by increasing the stress on the floating gate transistor. The increased stress can result in a source-to-drain short of the floating gate transistor. The notch also lowers the dopant concentration in the source adjacent the floating gate transistor. The low dopant concentration can result in erase errors during operation of the memory array.